*** snx.sfl	Wed Jun 11 15:07:37 2008
--- snxp1.sfl	Mon Jun 30 14:05:05 2008
***************
*** 1,9 ****
  /******************************************
!   Simple 16bit Non-Pipeline Processor (SN/X) V1.4.2
    Synthesizable SFL source code.
    (C)Copyright by Naohiko Shimizu, 1998-2008.
    All rights are reserved.
    Update informations:
      11-Jun-2008: minor change, use pc as an argument of ifetch stage.
      05-Jun-2008: Simplify executes.
      08-May-2008: Modified for Demonstration
--- 1,11 ----
  /******************************************
!   Simple 16bit Non-Pipeline Processor (SN/X) V1.4.2p1
    Synthesizable SFL source code.
    (C)Copyright by Naohiko Shimizu, 1998-2008.
    All rights are reserved.
    Update informations:
+     25-Jun-2008: stall condition adjust
+     18-Jun-2008: pipeline processor
      11-Jun-2008: minor change, use pc as an argument of ifetch stage.
      05-Jun-2008: Simplify executes.
      08-May-2008: Modified for Demonstration
***************
*** 28,34 ****
  %d dR3 opreg<9:8>
  %d dI 16#opreg<7:0>
  
! declare snx {
      input    inst<16> ;
      input    datai<16> ;
      output   datao<16> ;
--- 30,36 ----
  %d dR3 opreg<9:8>
  %d dI 16#opreg<7:0>
  
! declare snxp {
      input    inst<16> ;
      input    datai<16> ;
      output   datao<16> ;
*************** declare alu16 {
*** 76,82 ****
      instr_arg do_sr(a);
  }
  
! module snx {
      input    inst<16> ;
      input    datai<16> ;
      output   datao<16> ;
--- 78,84 ----
      instr_arg do_sr(a);
  }
  
! module snxp {
      input    inst<16> ;
      input    datai<16> ;
      output   datao<16> ;
*************** module snx {
*** 95,105 ****
      inc16    inc ;
      reg4     gr;
      alu16      alu;
!     reg      opreg<16>, mar<16>, regnum<2>;
!     sel      opr1<16>, opr2<16>, nxpc<16>, br_taken;
      instrself   dADD, dAND, dSLT, dNOT, dSR, dHLT,
          dLD, dST, dLDA, dBZ, dBAL;
!     instrself decode, opr1zero, start;
  
      instr_arg memory_write(adrs,datao);
      instr_arg memory_read(adrs);
--- 97,107 ----
      inc16    inc ;
      reg4     gr;
      alu16      alu;
!     reg      opreg<16>, mar<16>, regnum<2>, mdr<16>;
!     sel      opr1<16>, opr2<16>;
      instrself   dADD, dAND, dSLT, dNOT, dSR, dHLT,
          dLD, dST, dLDA, dBZ, dBAL;
!     instrself decode, opr1zero, start, br_taken, stall;
  
      instr_arg memory_write(adrs,datao);
      instr_arg memory_read(adrs);
*************** module snx {
*** 107,120 ****
  
      stage_name ifetch {
          task ift(pc) ;
-         task iftm() ;
      }
      stage_name exec {
          task exe(opreg) ;
      }
      stage_name memex {
!          task tstore(regnum, mar, pc);
!          task tload(regnum, mar, pc);
      }
  
      par{
--- 109,121 ----
  
      stage_name ifetch {
          task ift(pc) ;
      }
      stage_name exec {
          task exe(opreg) ;
      }
      stage_name memex {
!          task tstore(mar, mdr);
!          task tload(regnum, mar);
      }
  
      par{
*************** module snx {
*** 140,159 ****
    }
  
   stage ifetch {
           relay exec.exe(inst_read(pc).inst);
   }
  
   stage exec {
    par {
          decode();
!         br_taken = dBAL | (dBZ & opr1zero);
!         nxpc = inc.do(pc).out;
          opr1 = gr.reada(dR2).outa;
          if(opr1 == 0x0000) opr1zero();
          any {
            ITYPE & (dR3 == 0b00): opr2 = 0x0000;
            else : opr2 = gr.readb(dR3).outb;
            }
          any {
             ITYPE: alu.do_add(dI,opr2);
             dADD : gr.write(dR1, alu.do_add(opr1,opr2).out);
--- 141,172 ----
    }
  
   stage ifetch {
+    if(^stall & ^br_taken) par {
           relay exec.exe(inst_read(pc).inst);
+          relay ifetch.ift(inc.do(pc).out);
+    }
   }
  
   stage exec {
    par {
          decode();
!         if(dBAL | (dBZ & opr1zero)) br_taken();
          opr1 = gr.reada(dR2).outa;
          if(opr1 == 0x0000) opr1zero();
          any {
            ITYPE & (dR3 == 0b00): opr2 = 0x0000;
            else : opr2 = gr.readb(dR3).outb;
            }
+ /* make stall conditions */
+     if(memex.tload & (
+         (ITYPE & (dR3 .ne. 0b00) & (dR3 == regnum)) /* index read */
+        | ((dST | dBZ) & (dR2 == regnum)) /* ITYPE data read */
+        | ((dADD | dAND | dSLT) & (dR3 == regnum)) /* R type R3 read */
+        | ((dADD | dAND | dSLT | dSR | dNOT) & (dR2 == regnum)) /* R type R2 read */
+        | (dADD | dAND | dSLT | dSR | dNOT | dBAL | dLDA) /* GR write */ )
+       ) stall();
+ 
+     if(^stall) par {
          any {
             ITYPE: alu.do_add(dI,opr2);
             dADD : gr.write(dR1, alu.do_add(opr1,opr2).out);
*************** module snx {
*** 162,172 ****
             dNOT : gr.write(dR1, alu.do_not(opr1).out);
             dSR  : gr.write(dR1, alu.do_sr(opr1).out);
             dLDA : gr.write(dR2, alu.out);
!            dBAL : gr.write(dR2, nxpc);
          }
          any {
!           dLD: relay memex.tload(dR2, alu.out, nxpc);
!           dST: relay memex.tstore(dR2, alu.out, nxpc) ;
            br_taken:par {
                  wb(); relay ifetch.ift(alu.out);
                  }
--- 175,185 ----
             dNOT : gr.write(dR1, alu.do_not(opr1).out);
             dSR  : gr.write(dR1, alu.do_sr(opr1).out);
             dLDA : gr.write(dR2, alu.out);
!            dBAL : gr.write(dR2, pc);
          }
          any {
!           dLD: relay memex.tload(dR2, alu.out);
!           dST: relay memex.tstore(alu.out, opr1) ;
            br_taken:par {
                  wb(); relay ifetch.ift(alu.out);
                  }
*************** module snx {
*** 174,191 ****
                  hlt(); finish;
                  }
            else: par {
!                 wb(); relay ifetch.ift(nxpc);
                  }
            }
    }
   }
   stage memex {
    par {
     any {
!      memex.tstore: memory_write(mar,gr.reada(regnum).outa);
       memex.tload:  gr.write(regnum, memory_read(mar).datai);
       }
!    relay ifetch.iftm();
     wb();
    }
   }
--- 187,205 ----
                  hlt(); finish;
                  }
            else: par {
!                 wb(); finish;
                  }
            }
+      }
    }
   }
   stage memex {
    par {
     any {
!      memex.tstore: memory_write(mar,mdr);
       memex.tload:  gr.write(regnum, memory_read(mar).datai);
       }
!    finish;
     wb();
    }
   }