2c2
<   Simple 16bit Non-Pipeline Processor (SN/X) V1.4.2
---
>   Simple 16bit Non-Pipeline Processor (SN/X) V1.4.2p
6a7
>     18-Jun-2008: pipeline processor
31c32
< declare snx {
---
> declare snxp {
79c80
< module snx {
---
> module snxp {
98,99c99,100
<     reg      opreg<16>, mar<16>, regnum<2>;
<     sel      opr1<16>, opr2<16>, nxpc<16>, br_taken;
---
>     reg      opreg<16>, mar<16>, regnum<2>, mdr<16>;
>     sel      opr1<16>, opr2<16>;
102c103
<     instrself decode, opr1zero, start;
---
>     instrself decode, opr1zero, start, br_taken;
110d110
<         task iftm() ;
116,117c116,117
<          task tstore(regnum, mar, pc);
<          task tload(regnum, mar, pc);
---
>          task tstore(mar, mdr);
>          task tload(regnum, mar);
142a143
>    if(^br_taken & ^ memex.tload) par {
143a145,146
>          relay ifetch.ift(inc.do(pc).out);
>    }
146a150
>   if(^memex.tload)
149,150c153
< 	br_taken = dBAL | (dBZ & opr1zero);
<         nxpc = inc.do(pc).out;
---
> 	if(dBAL | (dBZ & opr1zero)) br_taken();
165c168
<            dBAL : gr.write(dR2, nxpc);
---
>            dBAL : gr.write(dR2, pc);
168,169c171,172
<           dLD: relay memex.tload(dR2, alu.out, nxpc);
<           dST: relay memex.tstore(dR2, alu.out, nxpc) ;
---
>           dLD: relay memex.tload(dR2, alu.out);
>           dST: relay memex.tstore(alu.out, opr1) ;
177c180
< 		wb(); relay ifetch.ift(nxpc);
---
> 		wb(); finish;
185c188
<      memex.tstore: memory_write(mar,gr.reada(regnum).outa);
---
>      memex.tstore: memory_write(mar,mdr);
188c191
<    relay ifetch.iftm();
---
>    finish;