SFL Tutorial 1: Basic structure of SFL
SFL describes the logic circuit as set of modules. The structure of a module is shown as following. Each definitions and/or descriptions can be eliminate but the order of the definitions should not be altered.
module module_name {
io_facility_defenitions
control_terminal_argument_definitions
core_behavior
control_behavior
stage_beharvior
}
Input and output of modules use external terminals:
|
Direction |
Terminal definitoin command |
Description |
|
Input |
input |
Data input terminal |
|
Output |
output |
Dta output terminal |
|
Bi-directional |
bidirect |
Data bi-directional terminal |
|
Input |
instrin |
Control input terminal |
|
Output |
instrout |
Control output terminal |
SFL has following facilities:
|
Facility definition |
Description |
|
instrself |
Control internal terminal |
|
sel |
Internal data terminal |
|
reg |
Register without reset |
|
reg_ws |
Register with power on set |
|
reg_wr |
Register with power on reset |
|
mem |
memory |
|
submodule_name |
Submodule instance definition |
SFL has following behavioral definitions:
|
Operation |
Description |
|
Unit operation |
Transfer a value to terminal, write to register, write to memory, state transition, activate control terminal, generate/transfer/terminate a job |
|
par |
Parallel activation of unit oprations. |
|
alt |
Conditional activation of unit operations with priority. |
|
any |
Conditional activation of unit operations without priority. (All of the matched operation will be activated in parallel) |
|
if |
Conditional activation of a unit operation. |
SFL operators:
|
Operator |
Description |
Operator |
Description |
|
^ |
Nagate |
| |
OR |
|
<n> |
Bit extraction |
@ |
EXOR |
|
<n:m> |
Bits extraction |
& |
AND |
|
/| |
Bitwise OR |
|| |
Bit concatination |
|
/& |
Bitwise AND |
+ |
Add |
|
/@ |
Bitwise EXOR |
== |
Equal |
|
n# |
Sign extention |
|
|
SFL provide bit operators and you can make bit twisting logic as Example-2.2.1.
Example-2.2.1 Bit extraction and concatination.
module testbitop {
input a<8>, b<8>;
output f<8>;
f = a<7> || (a<2:0>&b<7:5) || b<4:2> || a<6>;
}
The usage of sign extension operator is shown in Example-2.2.2.
Example-2.2.2 Sign extension.
module testsignext {
input a<4>;
output f<8>;
f = 8#a;
}
If you need to adjust bit width without sign extension, then use concatination as Example-2.2.3.
Example-2.2.3 Bit extentsion without sign extension
module testext {
input a<4>;
output f<8>;
f = 0b0000 || a;
}
Now we will start the tutorial exercises. Open a terminal window. Then we need to change current directory before starting the tutorials:
# cd; cd KISO1
3. par block
4. alt block
5. any block
9. Submodules
11. Register
12. Memory
13. Stage and Task
14. State Transision