module main; parameter STEP=10; integer i,j,vcd; reg p_reset, m_clock, intrq; reg [15:0] imem [0:1023]; reg [15:0] dmem [0:1023]; reg [15:0] inst,instq, datai; reg [7:0] led,sw; wire [15:0] datao,iadrs,iadrsq, adrs; wire inst_read,inst_readq, inst_write, memory_read,memory_write,wb,hlt; snxps cpu(p_reset,m_clock,inst, instq, datai, datao,iadrs, iadrsq, adrs, inst_read, inst_readq, inst_write, memory_read,memory_write,wb,hlt, intrq); /* initial begin intrq = 0; # (STEP*35) intrq = 1; # (STEP*3) intrq = 0; end */ always #(STEP/2) m_clock=~m_clock; always @(negedge m_clock) begin if((memory_read)&&(adrs[15]==0)) datai <= dmem[adrs]; end always @(negedge m_clock) begin if((memory_read)&&(adrs[15]==1)) datai <= {'h00,sw}; end always @(negedge m_clock) begin if (memory_write) if(adrs[15]==0) dmem[adrs] <= datao; else led <= datao[7:0]; end always @(negedge m_clock) begin if(inst_read) inst <= imem[iadrs]; end always @(negedge m_clock) begin if(inst_readq) instq <= imem[iadrsq]; end always @(negedge m_clock) begin if(cpu._task_exec_exe & ~cpu._task_memex_tload) begin $write("\nPC:%x ",cpu.pc); case (cpu.opreg[15]) 0: case (cpu.opreg[15:12]) 'h0: $write("add $%1d, $%1d, $%1d ",cpu.opreg[7:6],cpu.opreg[11:10],cpu.opreg[9:8]); 'h1: $write("and $%1d, $%1d, $%1d ",cpu.opreg[7:6],cpu.opreg[11:10],cpu.opreg[9:8]); 'h2: $write("sub $%1d, $%1d, $%1d ",cpu.opreg[7:6],cpu.opreg[11:10],cpu.opreg[9:8]); 'h3: $write("slt $%1d, $%1d, $%1d ",cpu.opreg[7:6],cpu.opreg[11:10],cpu.opreg[9:8]); 'h4: $write("not $%1d, $%1d ",cpu.opreg[7:6],cpu.opreg[11:10]); 'h5: $write("exr "); 'h6: $write("sr $%1d, $%1d ",cpu.opreg[7:6],cpu.opreg[11:10]); 'h7: $write("hlt "); endcase 1: case (cpu.opreg[7]) 0: case (cpu.opreg[15:12]) 'h8: $write("ld $%1d,%4d($%1d)",cpu.opreg[11:10],cpu.opreg[7:0],cpu.opreg[9:8]); 'h9: $write("st $%1d,%4d($%1d)",cpu.opreg[11:10],cpu.opreg[7:0],cpu.opreg[9:8]); 'ha: $write("lda $%1d,%4d($%1d)",cpu.opreg[11:10],cpu.opreg[7:0],cpu.opreg[9:8]); 'hd: $write("bri $%1d,%4d($%1d)",cpu.opreg[11:10],cpu.opreg[7:0],cpu.opreg[9:8]); 'he: $write("bz $%1d,%4d($%1d)",cpu.opreg[11:10],cpu.opreg[7:0],cpu.opreg[9:8]); 'hf: $write("bal $%1d,%4d($%1d)",cpu.opreg[11:10],cpu.opreg[7:0],cpu.opreg[9:8]); endcase 1: if(256-cpu.opreg[7:0]>=100) case (cpu.opreg[15:12]) 'h8: $write("ld $%1d,-%3d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'h9: $write("st $%1d,-%3d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'ha: $write("lda $%1d,-%3d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'hd: $write("bri $%1d,-%3d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'he: $write("bz $%1d,-%3d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'hf: $write("bal $%1d,-%3d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); endcase else if(256-cpu.opreg[7:0]>=10) case (cpu.opreg[15:12]) 'h8: $write("ld $%1d, -%2d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'h9: $write("st $%1d, -%2d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'ha: $write("lda $%1d, -%2d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'hd: $write("bri $%1d, -%2d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'he: $write("bz $%1d, -%2d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'hf: $write("bal $%1d, -%2d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); endcase else case (cpu.opreg[15:12]) 'h8: $write("ld $%1d, -%1d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'h9: $write("st $%1d, -%1d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'ha: $write("lda $%1d, -%1d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'hd: $write("bri $%1d, -%1d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'he: $write("bz $%1d, -%1d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); 'hf: $write("bal $%1d, -%1d($%1d)",cpu.opreg[11:10],256-cpu.opreg[7:0],cpu.opreg[9:8]); endcase endcase endcase $write(" -- "); end end always @(negedge m_clock) begin if(wb) #(STEP) $display("$0:%x $1:%x $2:%x $3:%x", cpu.gr.r0,cpu.gr.r1,cpu.gr.r2,cpu.gr.r3); if(hlt) begin $display("\nHALTED at %8d clock", $time/STEP); for(i=0; i<128; i=i+8) begin $write("%4x: ",i); for(j=0; j<8; j=j+1) $write("%x ",dmem[i+j]); $display; end $display("SW = %2x: LED = %2x", sw, led); $finish; end end initial begin $readmemh("snx.mem", imem); $readmemh("snx.dmem", dmem); if($value$plusargs("vcd=%d",vcd)) begin $dumpfile("snx.vcd"); $dumpvars(2,cpu); end m_clock=0; p_reset=0; sw = 'h34; #(STEP) p_reset=1; #(60000*STEP+(STEP/2)) $finish; end endmodule