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Fundamentals of Computer Design


Support page and NLS tools download

ICCD 2009, Lake Tahoe, CA, USA. Presentation Slide
Example for FPGA/NSL/SFL beginners.
  1. NSL PRIMER TUTORIAL
  2. FPGA Startup with SFL
  3. Make your own PC from scratch.
  4. Make your own game platform (Midway) from scratch.
Design flow with NSLCore:
NSLCore without license file can convert up to 500 lines of NSL. You can request for non profit license from OVERTONE CORP., Licensing site which allows you upto 2000 lines. After submitting your information, you will get an email with license file. Put the llicense file somewhere in your PC, and set environment variable NSL_LICENSE_FILE to designate the file. If you need full version or support, you can contact to Overtone Corp. for paid license.

You can download and install from following site, as
tar xzf nslcore-i386-linux-20100304.tar.gz -C / Or, you can use trial site.

  1. Binary Distribution
Related Items:

  • NSLspecE.txt NSL syntax description

  • SN/X CPU written with PapyrusUML

  • m8 CPU written with PapyrusUML

    The corresponding of class diagram and NSL syntax is followings:

  • SFL Tutorial text
  • Small 8bit Processor m8
  • Apple-I compatible system for Xilinx Spartan3/Spartan3E Starter Kit
  • POP11: PDP11/40m compatible CPU by Yoshihiro Iida
  • i8086 compatible CPU demo example It requires, nslcore, Icarus verilog, NASM, some other unix tools.
  • mcs6502 compatible CPU demo example It requires, nslcore, Icarus verilog, some other unix tools.
  • Z80 Compatible CPU DEMO EXAMPLE for Xilinx Spartan-3 Starter kit.
    It is a simple stopwatch output to a VGA color display. You can control the stopwatch with the tree buttomns of the starter kit.
    Bit file for Spartan-3 Starter Kit is here.
    Enjoy, Naohiko. 
    This archive is a demonstration of nslcore usage.

You need following tools to test:
  1. HDL converter nslcore (see http://www.ip-arch.jp/indexe.html ).
  2. Z80 C Compiler SDCC (see http://sdcc.sourceforge.net/ )
  3. Xilinx ISE 6.1 web-pack or later
  4. Cygwin and Development tools (see http://www.cygwin.com )
If you want to simulate the release, you will required to have Verilog compiler.
  5. Icarus Verilog (see http://www.icarus.com/eda/verilog/ )

The design is developped for Spartan-3 starter kit, and the UCF file was
written to use the board.
If you need to export for other boards, write your own ucf, etc.

After you installed all the above tools, you should have proper
execute path environment variable to run these tools under cygwin.
Then you can simply type:

 make ise

This command will setup a subdirectory for ISE.
Start ISE navigator and open project under the 'stopwatch' directory.

Next step will generate download bit file for your board.

 make new.bit

You can download using IMPACT the new bit file in which 
BRAM was modified with the embedded program.
  • RISC CPU SN/X
  • Pipeline CPU SP/X Source code
  • Pipeline CPU SN/Xp Source code
  • Simple 5 stage pipeline CPU SP/1 source code.
  • Icarus Verilog

    LiveCygwin packages:

    You need non profit license to make some packages. You can request for non profit license from this site, or contact to Overtone Corp. Place attached file to somewhere in your PC, and set an environment variable NSL_LICENSE_FILE to designate the file.

    EMM200 and support patch for HP-200LX

    Trial to make a good sound audio amplifier based on current amplify. I was inspired with JLH amp to make my original.

    Contact:

    IP Architecture Laboratory
    Naohiko Shimizu
    Email:nshimizu _at_ ip-arch.jp
    URL: http://www.ip-arch.jp/

    Spam mails should forward to mailagain@nissankyo.jp