// UML2SFL converter  Copyright (c) 2009 IP ARCH, Inc. All rights reserved.
	 // xmi  --- version 1.2 --- 
declare TanMIPS {
	  instrin start;
		  instrout memRd;
		  instrout memWt;
		input DataIn<32>;
		output DataOut<32>;
		output Address<32>;
		output Select<4>;
		
	instr_arg start (  );

		}

declare alu32 {
	  instrin exec;
		input inA<32>;
		input inB<32>;
		output Result<32>;
		input func<6>;
		
	instr_arg exec ( func,inA,inB );

		}

declare reg32 {
	  instrin regwt;
		  instrin regrdA;
		  instrin regrdB;
		output RegOutA<32>;
		output RegOUtB<32>;
		input RegIn<32>;
		input regA<5>;
		input regB<5>;
		input regW<5>;
		
	instr_arg regwt ( regW,RegIn );

	instr_arg regrdA ( regA );

	instr_arg regrdB ( regB );

		}

module TanMIPS {
	  instrin start;
		  instrout memRd;
		  instrout memWt;
		input DataIn<32>;
		output DataOut<32>;
		output Address<32>;
		output Select<4>;
		reg_wr PC<32>;
		reg InstReg<32>;
		reg oprA<32>;
		reg oprB<32>;
		reg DataRes<32>;
		alu32 alu;
	reg32 gr;
	
	proc_name ifetch ( PC );
	
	proc_name decode ( InstReg );
	
	proc_name exec ( oprA,oprB );
	
	proc_name memory ( DataRes );
	
	instr_arg memRd ( Address );
	
	instr_arg memWt ( Address,Select,DataOut );
	

		{
		/* common operations */
		}

		  instruct start {
			/* instrin start operation */
		}
		  proc ifetch {
			/* proc ifetch operation */
		}
		  proc decode {
			/* proc decode operation */
		}
		  proc exec {
			/* proc exec operation */
		}
		  proc memory {
			/* proc memory operation */
		}
		

		}
	 

module alu32 {
	  instrin exec;
		input inA<32>;
		input inB<32>;
		output Result<32>;
		input func<6>;
		

		{
		/* common operations */
		}

		  instruct exec {
			/* instrin exec operation */
		}
		

		}
	 

module reg32 {
	  instrin regwt;
		  instrin regrdA;
		  instrin regrdB;
		output RegOutA<32>;
		output RegOUtB<32>;
		input RegIn<32>;
		input regA<5>;
		input regB<5>;
		input regW<5>;
		

		{
		/* common operations */
		}

		  instruct regwt {
			/* instrin regwt operation */
		}
		  instruct regrdA {
			/* instrin regrdA operation */
		}
		  instruct regrdB {
			/* instrin regrdB operation */
		}
		

		}