NSL Language Specification  20110129 version Copyright IP ARCH, Inc.

Structure
Optional fuctionalities are described within < > 

NSL_FILE:
	declare_sentence
	| declare_struct
	| module_sentence

declare_sentence:

	declare module name < interface | simulation > {
	< parameter_declaration_list > 
	< input_output_elements_list > 
	}

declare_struct:
	struct struct_name  {
	< struct_elements_list > 
	} ;


module_sentence:
	module moudle_name {
	< internal_element_list > 
	< behavior_description_list >
	}

parameter_description_list:
	param_int parameter_name ;
	| param_str parameter_name ;

input_output_element_list:
	input terminal_list ;
	| output terminal_list;
	| inout terminal_list ;
	| func_in control_input_name( input/inout_terminal_list ) < : return_term > ;
	| func_out control_output_name( output/inout_terminal_list ) ;
	
struct_element_list:
	tag_name
	| tag_name<[bit_width]>
	| struct_element_list ; struct_element_list
	

return_term:
	 output/inout_terminal   % func_in

return_self_term:
	 wire_terminal


terminal_list:
	terminal_name
	| terminal_name<[bit_width]>
	| terminal_list , terminal_list

memory_list:
	memory_name
	| memory_name[word_number][bit_width]
	| memory_list , memory_list

submodule_name_list:
	submodule_name < [ num_instance ] >
	| submodule_name(parameter_list)
	| submodule_name_list , submodule_name_list

parameter_list:
	parameter_name = value
	| parameter_list , parameter_list

internal_element_list:
	wire terminal_list ;
	| reg  terminal_list < = initial_value >;
	| variable  terminal_list ;
	| mem  memory_list < = { initial_value_list } >;
	| integer  terminal_list ;
	| module_name  submodule_name_list ;
	| struct_name < wire | reg > struct_instance_list ;
	| state_name state_name_list ;
	| first_state state_name ;
	| label_name label_name_list ; % seq block only
	| proc_name  proc_name ( reg_terminal_list ) ;
	| func_self control_internal_name ( wire/outout/inout_terminal_list )  < : return_self_term > ;

struct_instance_list:
	struct_instance_name < = init_val >
	|struct_instance_list , struct_instance_list
 
behavior_description:
	{ <internal_element_declaration_list> behavior_description_list }
	| any { <internal_element_declaration_list> conditional_behavior_list }
	| alt { <internal_element_declaration_list> conditional_behavior_list }
	| seq { <internal_element_declaration_list> behavior_description_list }
	| if(expression) behavior_description < else behavior_description >
	| wire/output/variable/inoutterminal_name = expression ;
	| intvar = integer ;
	| regterminal_name := expression ;
	| regterminal_name++ ;
	| regterminal_name-- ;
	| struct_name := expression ;    % for reg type
	| struct_name.tag_name := expression ; % for reg type
	| struct_name = expression ;     %for wire type
	| struct_name.tag_name = expression ;  %for wire type
	| memory_terminal_name[address] := expression ;
	| control_internal_name(argument_list) ;
	| control_output_name(argument_list) ;
	| submodule_name.control_input_name(argument_list) ;
	| function control_input_name behavior_description
	| function control_internal_name behavior_description
	| function submodule_name.control_output_name behavior_description
	| return expression ;
	| proc proc_name behavior_description
	| proc_name(argument_list) ;
	| finish ;
	| state state_name behavior_description
	| goto state_name ;
	| goto label_name ;  % seq block only
	| label_name :       % seq block only
	| while(expression) { behavior_description_list }   % seq block only
	| for(behavior_description ; expression ; behavior_description) { behavior_description_list }   % seq block only
	| generate(int_assert ; expression ; int_assert) { behavior_description_list }

int_assert:
	terminal_name = integer;

behavior_description_list:
	behavior_description
	| behavior_description_list behavior_description_list 

conditional_behavior_list:
	expression : behavior_description
	| else : behavior_description

expression:
	value
	| expression & expression
	| expression | expression
	| expression ^ expression
	| expression + expression
	| expression - expression
	| expression * expression
	| expression >> integer
	| expression << integer
	| { expression , expression }
	| expression == expression
	| expression != expression
	| expression > expression
	| expression >= expression
	| expression < expression
	| expression <= expression
	| ~expression
	| &expression
	| |expression
	| ^expression
	| integer'(expression)
	| extended_bit_number # expression
	| (expression)<[bit_position]>
	| wire_terminal<[bit_position]>
	| reg_terminal<[bit_position]>
	| mem_terminal[address]<[bit_position]>
	| input_terminal<[bit_position]>
	| inout_terminal<[bit_position]>
	| output_terminal<[bit_position]>
	| proc_name
	| control_input_name
	| control_output_name
	| control_output_name(argument_list).input/inout_terminal<[bit_position]>
	| control_internal_name
	| control_internal_name(argument_list).wire_terminal<[bit_position]>
	| submodule_name.input_terminal<[bit_position]>
	| submodule_name.inout_terminal<[bit_position]>
	| submodule_name.output_terminal<[bit_position]>
	| submodule_name.control_output_name
	| submodule_name.control_input_name
	| submodule_name.control_input_name(argument_list).output_terminal<[bit_position]> ;
	| submodule_name.control_input_name(argument_list).control_output_name ;

value:
	integer'b binary_number
	| integer'o octal_number
	| integer'd decimal_number
	| integer'h hex_number
	| 0b binary_number
	| 0x hex_number

bit_width:
	integer

word_number:
	integer

bit_position:
	integer
	| integer : integer
	| expression

integer:
	decimal_number
	| integer + integer
	| integer - integer
	| integer * integer
	| integer / integer
	| integer & integer
	| integer | integer
	| integer ^ integer
	| integer >> integer
	| integer << integer
	| (integer)
	| integer && integer
	| integer || integer
	| integer > integer
	| integer >= integer
	| integer == integer
	| integer < integer
	| integer <= integer
	| integer != integer